| 2001/2002
Monthly Chapter Meeting Notices |
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September 2001 Meeting
Notice
(CANCELLED) |
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When/Where: |
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Tuesday, September 12, 2001. (CANCELLED) |
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Topic/Speaker: |
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Annual
Social and Business Planning Session |
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Details: |
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The September meeting of the Santa Clara Valley EMC
Society will be held at SGI in Mountain View, 1600 Amphitheatre Pkwy.,
building 40, in the Presentation Center above the lobby. The social
gathering will start at 5: 30 PM, and food and
drinks will be available at no charge. As usual after the summer break, this
meeting will be without any technical presentation.
(CANCELLED) |
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October
2001 Meeting Notice |
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When/Where: |
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Tuesday, October 9th, 2001. |
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Topic/Speaker: |
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"EFT Testing and
Common Pitfalls" - Doug Smith |
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Details: |
[
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The
October meeting of the Santa Clara Valley EMC Society will be held at SGI in
Mountain View, 1600 Amphitheatre Pkwy., building 40, in the Presentation
Center above the lobby. The social gathering will start at 5: 30 PM, and the
presentation starts at 7: 00 PM. A map with the location of the SGI campus
is available in this newsletter.
Doug Smith, will cover the background of EFT testing (IEC 61000- 4- 4) w
along with common pitfalls. Doug will also share some tips on the testing
process. Doug believes that all talks should have some entertainment value
and this talk is not an exception. War stories and demonstrations will be
used throughout the talk.
One of these covers a common mistake that some testing labs make that can
nearly double the stress on the EUT. If you have an EFT Burst Generator what
do you do with it when it is not being used (probably most of the time
unless you work for a test lab)? Doug will cover some test / debug
techniques using an EFT generator that have nothing to do with EFT, such as
solving ESD problems and measuring noise margins
at the PWB and circuit trace level.
About the presenter:
Mr. Smith received a B. S. E. E. degree from Vanderbilt University in 1969
and an M. S. E. E. degree from the California Institute of Technology in
1970. In 1970, he joined AT& T Bell Laboratories as a Member of Technical
Staff. He retired in 1996 as a Distinguished Member of Technical Staff. From
February 1996 to April 2000 he was Manager of EMC Development and Test at
Auspex Systems in Santa Clara, CA. Mr. Smith currently is an independent
consultant specializing in high frequency measurements, circuit/ system
design and verification, switching power supply noise and specifications,
EMC, and immunity to transient noise. He is a Senior Member of the IEEE and
a member of the IEEE EMC Society Board of Directors.
His technical interests include high frequency effects in electronic
circuits. He has been granted over 15 patents, several on measurement
apparatus. Mr. Smith has lectured at Vanderbilt University, AT& T Bell Labs,
and at many public and private seminars on high frequency measurements,
circuit design, ESD, and EMC. He is
author of the book High Frequency Measurements and Noise in Electronic
Circuits and is currently working on his second book. |
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November
2001 Meeting Notice |
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When/Where: |
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Tuesday, November 13th, 2001. |
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Topic/Speaker: |
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"CEM Methods for
System-Level EMC Design" - Fred German |
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Details:
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Ever-increasing clock speeds have greatly increased electromagnetic
emissions from computer processors and ASICs.. Consequently the containment
of electromagnetic radiation has become a major factor in the physical
design of electronic systems. The "test and fix" approach solving EMC
problems in the lab after a prototype is built is not acceptable in today�s
highly competitive market led environment. Time to market pressures mean
that designs must pass regulatory and corporate requirements the first time.
Recent advances in computational electromagnetics (CEM) now permits the
rapid characterization of EMC performance of electronic equipment at the
system level. In this presentation, an overview of the various CEM methods
available for system-level EMC design will be. Realistic case studies will
be presented showing their effectiveness in the product design cycle.
About the Presenter:
Fred German is a Senior Consulting Engineer with Flomerics, Inc. in their
Electromagnetics Division. Fred provides consulting and support in the area
of computational electromagnetics for EMC and antenna design . He has been
involved in the application of numerical methods to electromagnetic design
problems since 1987. |
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December
2001 Meeting Notice |
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When/Where: |
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Tuesday, December 11th, 2001. |
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Topic/Speaker: |
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"SCV EMC Society,
meeting jointly with the SCV Product Safety Society" |
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Details: |
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On
December 11 we will be having our annual social gathering, normally held in
September of each year.
Please come and join friends and colleagues for a relaxed evening of food,
drink, conversation, and live entertainment, all of which will be provided
free of charge.
To EMC Society members we will be passing out (and later collecting) ballots
so that you may vote for officers to serve in calendar 2002.
Hope to see you there!
THIS GATHERING WILL BE
HELD IN THE BUILDING 40 OZONE CAFE FROM 5:30PM - 8:30PM |
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January
2002 Meeting Notice |
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When/Where: |
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Tuesday, January 8th, 2002. |
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Topic/Speaker: |
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"Circuit Design
Trends and Challenges in Multi-Gigahertz Microprocessors" |
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Details: |
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Moore's law drives the VLSI technology to smaller transistors and higher
clock frequencies. As VLSI process features shrink deep into submicron
territory, leading microprocessor designs have broken the 1GHz limit. This
creates new challenges for designers at both the chip and the system level.
This presentation will review the trends in submicron design and present the
challenges ahead.
At the chip level, the metal interconnects are
getting slower with every generation. Copper interconnects and low-K
dielectrics will only temporarily ease the burden. To make up for this
slowdown and still meet the increasing frequency targets, designers employ
aggressive design techniques, like domino logic. This provides higher speed,
but with a higher power dissipation. Another emerging technique for
achieving higher frequencies is to use dual Vt transistors. The power supply
voltage levels are dropping with every process generation, while capacitive
and inductive coupling are becoming an increasing concern.
At the system level, bus interface speeds are
increasing with every generation. The bus design is shifting from a common
clock timing mode to a source-synchronous design that offers wider timing
margins. Flip-chip packaging provides better power distribution and shorter
interconnects.
About the Presenter:
Stefan Rusu is a Principal Engineer in Intel's Enterprise Products Group
leading the technology and special circuits design team for the entire
Itanium(tm) Processor Family. He received an M.S. degree in Electrical
Engineering from the Polytechnic Institute in Bucharest, Romania. He first
joined Intel Corporation in 1984 working on data communications integrated
circuits. In 1988 he joined Sun Microsystems working on microprocessor
design with focus on clock and power distribution, packaging, standard cell
libraries, CAD and circuit design methodologies. He re-joined Intel
Corporation in 1996 to drive the clock and power distribution, cell library,
I/O buffers and package design for the first Itanium(tm) microprocessor. His
technical interests are high-speed clocking, power distribution, I/O
interfaces, low-power design and high-speed circuit design techniques. He
has published numerous technical papers and currently holds 12 U.S. patents
with several more pending. He has been a member of the ESSCIRC Technical
Program Committee since 1998. |
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February
2002 Meeting Notice |
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When/Where: |
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Tuesday, February 12th, 2002. |
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Topic/Speaker: |
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"Cost
Effective PCB Design" - John
Howard |
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Details: |
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The subject of this presentation will be some of the features in multilayer
printed circuit boards which seriously contribute to poor Electromagnetic
Compatibility and signal integrity. Featured will be some very common
routing practices which are not much of a problem for some signals but are
very much a problem for others. Finite element analysis will be presented to
highlight these issues from very modest MHz to significant GHz. Finite
element method tools readily display the solutions to these problem
features. Comprehension about the hazards from these common board
construction practices will contribute to better quality signals and fewer
PC board turns. This is the "engineered" solution to reducing PCB design
cost, and schedule impact.
About the Presenter:
John Howard is currently working as a Independent Consultant with
specific expertise in the area of Electromagnetic Compatibility and EMC
management. His background includes work as a Electronics Technician prior
to earning BSEE and MSEE degrees. He has worked as a hardware engineer,
engineering manager, and scientific researcher for several bay area
companies including Hewlett Packard, Motorola/Four Phase Systems, Lockheed
Research, Compaq/Tandem Computers, and others. During the past twenty plus
years John has become a leader in the field of EMC. He has authored or
co-authored several technical papers on the subject of design for EMC
compliance.
John is a Senior Member of the IEEE and past chairman
of the Santa Clara Valley IEEE EMC Society. John has been teaching a variety
of EMC related courses around the USA under continuous sponsorship by the
University of Wisconsin at Milwaukee for the past seven years. He regularly
presents EMC courses for the SMCBA in Australia and many other companies or
organizations around the world. He is a NARTE registered professional EMC
engineer and a member of the dB Society. His outside interests include
membership in Mensa, general aviation, and classical music. |
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